1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for processing a semiconductor substrate.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In the fabrication of metal-oxide-semiconductor (“MOS”) transistors, source and drain regions may be doped to an opposite conductivity type (either n-type or p-type) than the substrate. N-type source/drain regions may be used to form n-channel transistors and p-type source/drain regions may be used to form p-channel transistors. In complementary MOS (“CMOS”) circuits, however, both n-channel and p-channel transistors are formed within the same substrate. Consequently, wells may be formed by selectively doping the region of the substrate underlying the subsequently formed gate conductors to allow a substrate of either conductivity type to be used. In general, wells may be doped to an opposite conductivity type than that of the source and drain regions. In this manner, n-channel transistors may be formed in p-type wells, while p-channel transistors may be formed in n-type wells. In some cases, additional dopants may be introduced into the substrate to form channel dopant regions within the wells. Preferably, the channel dopant regions may be the same conductivity type as the wells in which they reside. In general, channel dopant regions may be used to prevent punch-through and short channel effects of subsequently formed transistors.
In addition, the fabrication of MOS transistors typically includes the formation of isolation structures between the active areas of the device. In general, the isolation structures may define the field regions of the semiconductor substrate, while the area including the well regions and channel dopant regions may define the active areas of the substrate. One isolation technology used in the fabrication of integrated circuits involves local oxidation of silicon (“LOCOS”). In LOCOS processes, an oxide layer may be grown upon a silicon substrate and a silicon nitride (“nitride”) layer may be arranged upon the oxide layer. The surfaces of the field regions upon the silicon substrate may then be exposed by etching portions of the nitride layer and the oxide layer. Remaining portions of the nitride layer and oxide layer may cover active regions of the silicon substrate, thereby serving as a mask to prevent oxidation of these regions in subsequent steps. An implant may then be performed in the field region to create a channel-stop doping layer and the exposed portion of the silicon substrate within the field region may be oxidized. By growing a thick oxide film within isolation (or field) regions pre-implanted with a channel-stop dopant, LOCOS processing may help prevent the establishment of parasitic channels in the field regions.
Although LOCOS has remained a popular isolation technology, the LOCOS process described above has several problems. When growing the field oxide, oxide growth should ideally be contained within the field region. In reality, however, some oxide growth may occur in a lateral direction, causing the field oxide to grow under and lift the edges of the nitride layer. Because the shape of the field oxide at the nitride edges is that of a slowly tapering wedge that merges into the pad oxide, the wedge is often described as a bird's beak. In many instances, formation of the bird's beak can cause unacceptable encroachment of the field oxide into the active regions. In addition, the high temperatures associated with field oxide growth often cause the pre-implanted channel-stop dopant to migrate towards adjacent active regions. An increase in the dopant concentration near the edges of the field oxide can create a reduction in the drain current, an outcome that is often described as the narrow-width effect. Furthermore, thermal oxide growth is significantly less in small field regions (i.e., field areas of narrow lateral dimension) than in large field regions. Because of this reduction in oxide growth, an undesirable phenomenon known as the field-oxide-thinning effect may occur in small field regions. Field-oxide-thinning can produce problems with respect to field threshold voltage magnitudes, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Despite advances made to decrease the bird's beak, channel-stop encroachment and non-planarity problems, it appears that LOCOS technology is still inadequate for sub-micron technologies. Many of the problems associated with LOCOS technology may be alleviated by an isolation technique known as trench isolation. A trench isolation fabrication process typically includes an initial step in which a trench is etched within a silicon substrate. The trench may then be filled with a dielectric, such as silicon dioxide. Some trench isolation processes also include an intermediate step of growing oxide on the trench floor and sidewalls before filling the trench with the dielectric. After the trench is filled, the upper surface of the dielectric may then be made coplanar with the upper surface of the silicon substrate to complete the fabrication of the isolation structure. The trench isolation process eliminates many of the problems of LOCOS techniques, including bird's beak and channel-stop dopant redistribution. Trench isolation processes are also better suited than LOCOS processes for isolating densely spaced active devices having field regions less than one micron wide. In addition, trench isolation structures formed by trench isolation processes may be fully recessed, offering at least the potential for a planar surface. Moreover, field-oxide thinning in narrow isolation spaces is less likely to occur when using a trench isolation process.
Despite their many advantages over LOCOS techniques, trench isolation processes nevertheless have their own set of drawbacks. In particular, the threshold voltage magnitude, VT, of a transistor separated by trench isolation structures may decrease as the width of the transistor decreases. Such a phenomenon is sometimes referred to as the inverse narrow width effect (“INWE”). In contrast, the threshold voltage magnitude of transistors separated by isolation regions fabricated from techniques other than trench isolation processes may increase as the width of the transistor decreases. It is postulated that the INWE may be related to fields generated by transistors and concentrated at sharp corners between the silicon substrate and trench isolation structures. In addition or alternatively, the INWE may be influenced by the diffusion of dopant atoms from the silicon into the isolation structures, thereby reducing the dopant concentration of the channel dopant regions of the transistors. In other cases, the isolation regions may extend below the active region of the silicon, forming a channel along the side of the active region. Each of these conditions, either independently or in combination, may result in a decrease of the threshold voltage magnitude of a subsequently formed transistor.
A threshold voltage magnitude lower than its design value is undesirable because leakage current is typically increased as threshold voltage magnitude is decreased. Conversely, high threshold voltage magnitudes may have an undesirable effect on performance of the circuit, particularly at low supply voltages. Therefore, it may be beneficial to maintain transistor threshold voltage magnitudes within predetermined ranges. Consequently, as transistor widths continue to decrease and the use of trench isolation techniques becomes more prevalent, methods for adjusting the threshold voltage magnitude of transistors will become increasingly necessary. One method of adjusting the threshold voltage magnitude of a transistor is to implant a greater concentration of impurities into the channel dopant region of a subsequently formed transistor. However, the INWE is dependent on the width of the transistor and therefore, relatively wide transistors may not be affected by the INWE as much as the narrow-width transistors. Implanting an increased concentration of impurities into channel dopant regions of subsequently formed relatively wide transistors may lead to an unnecessarily large threshold voltage magnitude for those transistors, which may degrade their performance. Therefore, the implantation of a greater concentration of impurities into channel dopant regions may be appropriate only for the narrow-width transistors.
As a result, the implantation of additional impurities may be cumbersome, time-consuming, and costly when transistors of different conductivity types and sizes are fabricated into the same integrated circuit. For example, narrow-width CMOS transistors (i.e. transistors with a width of less than approximately 1 micron) are sometimes fabricated along with relatively wide CMOS transistors (i.e. transistors with a width of greater than approximately 1 micron) within the same integrated circuit. A fabrication process for such a device may require at least four masking layers in order to form channel dopant regions with the appropriate impurity concentrations such that transistors with the appropriate threshold voltage magnitudes may be subsequently formed. For instance, the fabrication process may require a different masking layer for the formation of each channel dopant region (e.g., narrow NMOS, wide NMOS, narrow PMOS, and wide PMOS channel dopant regions). Alternatively, the fabrication process may include forming the PMOS transistor channel dopant regions with one masking layer and the NMOS transistor channel dopant regions with another masking layer, and then using two separate masking layers to implant additional impurities to increase or decrease the threshold voltage magnitudes of the subsequently formed transistors.
Accordingly, it would be advantageous to develop a method for forming a CMOS integrated circuit with differing transistor widths and conductivity types and comparable threshold voltage magnitudes. In particular, it would advantageous to form such an integrated circuit using fewer masking layers than conventional methods.